/*
 * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved. All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 */
#ifndef _AR0132_RCCB_SETTING_H_
#define _AR0132_RCCB_SETTING_H_

#define AR0231_VER_7 7
#define AR0231_VER_6 6
#define AR0231_VER_4 4

/* Fine Integration time for 3-exp HDR */
#define AR0132_FINE_INTEG_TIME(hts) (hts - 276)

#define AR0231_ACTIVE_H 1280
#define AR0231_ACTIVE_V 960

#define AR0132_HTS 1650       // must confirm to aptina
#define AR0132_VTS_30FPS 990 // must confirm to aptina

#define AR0132_PCLK 72000000 // Hz,if MCLK 24MHZ

typedef enum {
  ISC_AR0132_30FPS = 0, // default fps
  ISC_AR0132_NUM_FPS
} SupportedFrameRateAR0132;

typedef struct {
  unsigned int hts;
  unsigned int vts;
  const unsigned char *settings;
} TimingSettingAR0132;

static const unsigned char ar0132_raw12_default[] = { // 1280 *960  30fps
    'w', 4, 0x30, 0x1A, 0x10, 0xD8,                   // RESET_REGISTER
    'd', 0x27, 0x01,                                  // Delay 255ms

    // HiDy Parallel Full Resolution
    // HDR Mode Setup
    'w', 4, 0x30, 0x1A, 0x10, 0xD8,
    'w', 4, 0x30, 0x82, 0x00, 0x28,

    // Column Retriggering at start up
    'w', 4, 0x30, 0xB0, 0x13, 0x00,
    'w', 4, 0x30, 0xD4, 0xE0, 0x07,
    'w', 4, 0x30, 0xBA, 0x00, 0x08,

    'w', 4, 0x30, 0x58, 0x00, 0x3F,
    'w', 4, 0x31, 0x12, 0x02, 0xA0,
    'w', 4, 0x30, 0x32, 0x00, 0x00,



    //'w', 4, 0x30, 0x7C, 0x00, 0x2A,
    //'w', 4, 0x30, 0x80, 0x00, 0x03,
    //-------------------------------
    'w', 4, 0x30, 0x32, 0x00, 0x00,

    'w', 4, 0x30, 0x12, 0x00, 0x02,
    'w', 4, 0x30, 0x16, 0x00, 0x02,
    // Y_Addr_Start
    'w', 4, 0x30, 0x02, 0x00, 0x02,
    // X_Addr_Start
    'w', 4, 0x30, 0x04, 0x00, 0x00,
    // Y_Addr_End 960
    'w', 4, 0x30, 0x06, 0x03, 0xC1,
    // X_Addr_End 1280
    'w', 4, 0x30, 0x08, 0x04, 0xFF,
    // Frame_Length_Lines
    'w', 4, 0x30, 0x0A, (AR0132_VTS_30FPS >> 8) & 0xff, AR0132_VTS_30FPS & 0xff,
    // Line (Row) time
    'w', 4, 0x30, 0x0C, (AR0132_HTS >> 8) & 0xff, AR0132_HTS & 0xff,

    // Enable Parallel Mode
    'w', 4, 0x30, 0x1A, 0x10, 0xD8,
    'w', 4, 0x31, 0xD0, 0x00, 0x01,

    'w', 4, 0x30, 0x2C, 0x00, 0x01,

    // PLL Enabled 24Mhz to 72Mhz
    // VT_PIX_CLK_DIV, TV_SYS_CLK_DIV, PRE_PLL_CLK_DIV, PLL_MULTIPLIER
    'w', 10, 0x30, 0x2A,
    0x00, 0x0A, // VT_PIX_CLK_DIV,
    0x00, 0x01, //TV_SYS_CLK_DIV
    0x00, 0x02, //PRE_PLL_CLK_DIV
    0x00, 0x3C, //PLL_MULTIPLIER

    'w', 4, 0x30, 0xb0, 0x13, 0x00,
    'd', 0x27, 0xc8, // Delay 200ms

    'w', 4, 0x30, 0x1A, 0x10, 0xDC,
    'w', 4, 0x30, 0x28, 0x00, 0x00,
    'w', 4, 0x30, 0x6e, 0x9e, 0x10,

    'w', 4, 0x30, 0x64, 0x19, 0x82, // SMIA_TEST, enable top embedded data

    'w', 4, 0x30, 0x58, 0x00, 0x3F,

    // cmd_StreamOn
    //'w', 4, 0x30, 0x1A, 0x10, 0xDC,
    'w', 4, 0x31, 0x4A, 0xFF, 0x7F,
    'e'
};

static const unsigned char ar0132_raw12_comp_1280x960_30fps[] = {'e'};

static const unsigned char ar0132_enable_streaming[] = {
    4, 0x30, 0x1A, 0x10, 0xDC, // RESET_REGISTER
};

static const TimingSettingAR0132 ar0132_timing[ISC_CONFIG_AR0231_NUM_FORMAT] = {
    { AR0132_HTS, AR0132_VTS_30FPS, ar0132_raw12_comp_1280x960_30fps }
};

#endif /* _AR0231_RCCB_SETTING_H_ */
